HYB18T256802AF-5 Ver la hoja de datos (PDF) - Infineon Technologies
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HYB18T256802AF-5 Datasheet PDF : 33 Pages
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HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
4.5 IDD Measurement Conditions (cont’d)
For testing the IDD parameters, the following timing parameters are used:
Parameter
Symbol
CAS Latency
CLmin
Clock Cycle Time
tCKmin
Active to Read or Write delay
tRCDmin
Active to Active / Auto-Refresh command period
tRCmin
Active bank A to Active bank B command delay
x4 & x8 tRRDmin
Active to Precharge Command
tRASmin
Precharge Command Period
tRPmin
Auto-Refresh to Active / Auto-Refresh command period
tRFCmin
Average periodic Refresh interval
tREFI
PC2-3200R “-5“
3-3-3
3
5
15
60
7.5
45
15
105
7.8
PC2-4300R “-3.7” Unit
4-4-4
4
tCK
3.75
ns
15
ns
60
ns
7.5
ns
45
ns
15
ns
105
ns
7.8
µs
4.6 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1).
Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The cur-
rent consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long
a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State min. typ. max. Unit
Enabled ODT current per DQ
added IDDQ current for ODT enabled;
ODT is HIGH; Data Bus inputs are FLOATING
A6 = 0, A2 = 1 5
IODTO
A6 = 1, A2 = 0 2.5
6 7.5 mA/DQ
3 3.75 mA/DQ
Active ODT current per DQ
A6 = 0, A2 = 1 10 12 15 mA/DQ
added IDDQ current for ODT enabled;
IODTT
ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
A6 = 1, A2 = 0 5
6 7.5 mA/DQ
note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
Preliminary
16
Rev. 0.85, 2004-04
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