GAL20V8B-20QPI Ver la hoja de datos (PDF) - Lattice Semiconductor

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GAL20V8B-20QPI

High Performance E2CMOS PLD Generic Array Logic™

Lattice Semiconductor 

Specifications GAL20V8

Complex Mode

In the Complex mode, macrocells are configured as output only or signs requiring eight I/Os can be implemented in the Registered

I/O functions.

mode.

Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product

common 20L8 and 20P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and

each macrocell.

13 are always available as data inputs into the AND array.

Up to six I/Os are possible in this mode. Dedicated inputs or outputs The JEDEC fuse numbers including the UES fuses and PTD fuses

can be implemented as subsets of the I/O function. The two outer are shown on the logic diagram on the following page.

most macrocells (pins 15 & 22) do not have input capability. De-

XOR

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 16 through Pin 21 are configured to this function.

XOR

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 15 and Pin 22 are configured to this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

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