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M27V401

4 Mbit (512Kb x 8) Low Voltage UV EPROM and OTP EPROM

STMicroelectronics 

M27V401

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)

Symbol

Parameter

Test Condition

Min

Max

ILI

Input Leakage Current

0V ≤ VIN ≤ VCC

±10

ILO Output Leakage Current

0V ≤ VOUT ≤ VCC

±10

ICC Supply Current

E = VIL, G = VIL, IOUT = 0mA,

15

f = 5MHz, VCC ≤ 3.6V

ICC1 Supply Current (Standby) TTL

E = VIH

1

ICC2 Supply Current (Standby) CMOS

E > VCC – 0.2V, VCC ≤ 3.6V

20

IPP Program Current

VPP = VCC

10

VIL Input Low Voltage

–0.3

0.8

VIH (2) Input High Voltage

2

VOL Output Low Voltage

IOL = 2.1mA

Output High Voltage TTL

VOH

Output High Voltage CMOS

IOH = –400µA

IOH = –100µA

2.4

VCC –0.7V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

2. Maximum DC voltage on Output is VCC +0.5V.

VCC + 1

0.4

Unit

µA

µA

mA

mA

µA

µA

V

V

V

V

V

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85°C; VCC = 3.3V ± 10%; VPP = VCC)

M27V401

Symbol

Alt

Parameter

Test Condition

-120

-150

Unit

Min Max Min Max

tAVQV

tACC Address Valid to Output Valid

E = VIL, G = VIL

120

150 ns

tELQV

tCE Chip Enable Low to Output Valid

G = VIL

120

150 ns

tGLQV

tOE Output Enable Low to Output Valid

E = VIL

60

80 ns

tEHQZ (2)

tDF Chip Enable High to Output Hi-Z

G = VIL

0 50 0 50 ns

tGHQZ (2)

tDF Output Enable High to Output Hi-Z

E = VIL

0 50 0 50 ns

tAXQX

tOH

Address Transition to Output

Transition

E = VIL, G = VIL

0

0

ns

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

2. Sampled only, not 100% tested.

Two Line Output Control

Because EPROMs are usually used in larger

memory arrays, this product features a 2 line con-

trol function which accommodates the use of mul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power dissipation,

b. complete assurance that output bus contention

will not occur.

For the most efficient use of these two control

lines, E should be decoded and used as the prima-

ry device selecting function, while G should be

made a common connection to all devices in the

array and connected to the READ line from the

system control bus. This ensures that all deselect-

ed memory devices are in their low power standby

mode and that the output pins are only active

when data is required from a particular memory

device.

5/15

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