AD7822BRUZ-REEL71 Ver la hoja de datos (PDF) - Analog Devices
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AD7822BRUZ-REEL71 Datasheet PDF : 28 Pages
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AD7822/AD7825/AD7829
CIRCUIT INFORMATION
CIRCUIT DESCRIPTION
The AD7822/AD7825/AD7829 consist of a track-and-hold
amplifier followed by a half-flash analog-to-digital converter.
These devices use a half-flash conversion technique where one
4-bit flash ADC is used to achieve an 8-bit result. The 4-bit flash
ADC contains a sampling capacitor followed by 15 comparators
that compare the unknown input to a reference ladder to
achieve a 4-bit result. This first flash (that is, coarse conversion)
provides the four MSBs. For a full 8-bit reading to be realized,
a second flash (that is, fine conversion) must be performed to
provide the four LSBs. The 8-bit word is then placed on the data
output bus.
Figure 6 and Figure 7 show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes
into hold mode and holds the analog input for 120 ns. This is
the acquisition phase, as shown in Figure 6, when Switch 2 is in
Position A. At the point when the track-and-hold returns to its
track mode, this signal is sampled by the sampling capacitor,
as Switch 2 moves into Position B. The first flash occurs at this
instant and is then followed by the second flash. Typically, the
first flash is complete after 100 ns, that is, at 220 ns; and the end
of the second flash and, hence, the 8-bit conversion result is
available at 330 ns (minimum). The maximum conversion time
is 420 ns. As shown in Figure 8, the track-and-hold returns to
track mode after 120 ns and starts the next acquisition before
the end of the current conversion. Figure 10 shows the ADC
transfer function.
REFERENCE
R16
15
DB7
SW2
A
VIN
T/H 1
R15
14
B SAMPLING
HOLD
CAPACITOR
DB6
DB5
DB4
R14
13
DB3
DB2
R13
DB1
1
DB0
R1
TIMING AND
CONTROL
LOGIC
Figure 6. ADC Acquisition Phase
REFERENCE
R16
15
SW2
A
VIN
T/H 1
R15
14
B SAMPLING
HOLD
CAPACITOR
R14
13
R13
1
R1
TIMING AND
CONTROL
LOGIC
Figure 7. ADC Conversion Phase
TRACK
120ns
HOLD
CONVST
t2
t1
EOC
TRACK
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
HOLD
CS
t3
RD
DB0 TO DB7
VALID
DATA
Figure 8. Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAM
Figure 9 shows a typical connection diagram for the AD7822/
AD7825/AD7829. The AGND and DGND are connected
together at the device for good noise suppression. The parallel
interface is implemented using an 8-bit data bus. The end of
conversion signal (EOC) idles high, the falling edge of CONVST
initiates a conversion, and at the end of conversion the falling
edge of EOC is used to initiate an interrupt service routine
(ISR) on a microprocessor (see the Parallel Interface section for
more details.) VREF and VMID are connected to a voltage source
such as the AD780, and VDD is connected to a voltage source
that can vary from 4.5 V to 5.5 V (see Table 5 in the Analog Input
section). When VDD is first connected, the AD7822/AD7825/
AD7829 power up in a low current mode, that is, power-down
mode, with the default logic level on the EOC pin on the
AD7822 and AD7825 equal to a low. Ensure the CONVST line is
not floating when VDD is applied, because this can put the
AD7822/AD7825/AD7829 into an unknown state.
Rev. C | Page 10 of 28
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