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M5M410092BFP

Overview of 3D-RAM and Its Functional Blocks

MITSUBISHI ELECTRIC  

MITSUBISHI

ELECTRONIC DEVICE GROUP

Rev. 1.03

3D-RAM (M5M410092B)

3D-RAM Functional Blocks

The 3D-RAM has five major functional blocks in:

DRAM banks, Video Buffers, Pixel Buffer, Global

Bus, and Pixel ALU. The following sections

provide a quick overview of each of these

functional blocks. Chapter 3 describes details of

the Pixel ALU operations, Chapter 4 presents

specifics of the DRAM operations, and Chapter 5

provides examples of parallelism between the

Pixel ALU operations and the DRAM operations.

Now, to give readers a better grasp of these

functional blocks, we first describe the memory

units on which these functional blocks operate.

Block, Page, and Page Group

A word has 32 bits and is the unit of data

operations within the Pixel ALU and between the

Pixel ALU and Pixel Buffer. When the Pixel ALU

accesses the Pixel Buffer, not only a block

address needs to be specified but also a word has

to be identified. Since there are eight blocks in the

Pixel Buffer and eight words in a block, the upper

three bits of the input pins PALU_A designate the

block, and the lower three bits select the word.

The data in a word is directly mapped to

PALU_DQ[31:0] in corresponding order. That is, bit

0 of the word is mapped to PALU_DQ0, bit 1 to

PALU_DQ1, and so on.

Although an ALU write operation operates on one

word at a time, each of the four bytes in a word

may be individually masked. The mapping is also

direct and linear: byte 0 is PALU_DQ[7:0], byte 1

PALU_DQ[15:8], byte 2 PALU_DQ[23:16], and byte

3 PALU_DQ[31:24].

A block has 256 bits and is the unit of memory

operations between a DRAM bank and the Pixel

Buffer over the Global Bus. The input pins

DRAM_A selects a block from the Pixel Buffer and

a block from a page of a DRAM bank. The DRAM

operations on block data are Unmasked Write

Block (UWB), Masked Write Block (MWB), and

Read Block (RDB). These operations are

described in detail on page 44, “Description of

DRAM Operations.”

A page in a DRAM bank is organized into 10 x 4

blocks. Since a block has 256 bits, a page has

10,240 bits. There are four DRAM banks in a

3D-RAM chip, the pages of the same page

address from all four DRAM banks compose a

page group. Therefore, a page group has 20 x 8

blocks.

Note in Figure 1.3, the block and page are

purposely drawn as rectangular shapes. The user

may relate these to a tiled frame buffer memory

organization. For example, if the display resolution

is 1280 x 1024 x 8, then a (32-bit) word contains

four pixels. Since a block may be viewed as

having 2 x 4 words, it contains 8 x 4 pixels. A page

is organized into 10 x 4 blocks, so it contains 80 x

16 pixels, and a page group holds 160 x 32 pixels.

Finally, a screen is composed of 8 x 32 page

groups. The advantage of such a frame buffer

memory organization is the minimization of page

miss penalty. 3D objects frequently occupy

portions of multiple scan lines. Since in this case a

page contains 80 x 16 pixels instead of 10,240 x 1

pixels, page miss is reduced. When an object

extends beyond a page boundary, bank

interleaving allows hidden precharge and

uninterrupted memory access. Details of the

various frame buffer memory organizations using

3D-RAMs are discussed in Chapter 6.

On the other hand, to support screen refresh, the

Video Buffer must output pixel data one scan line

at a time. The internal organization of a page also

allows data to be transferred from a page to the

Video Buffer, one of the sixteen scan lines of 80

bytes long each at a time. See the section “Video

Buffers” on page 7 for a summary and the section

“Video Transfer (VDX)” on page 46 for full details.

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