DS21372T Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21372T

3.3V Bit Error Rate Tester (BERT)

Dallas Semiconductor -> Maxim Integrated 

DS21372

PIN SYMBOL TYPE DESCRIPTION

24

RL

25 RDATA

I Receive Load. A positive-going edge loads the previous 32 bits of data

received at RDATA into the Pattern Receive Registers. RL is logically

OR’ed with control bit PCR.3. Should be tied to VSS if not used.

I Receive Data. Received NRZ serial data, sampled on the rising edge of

RCLK.

26 RDIS

I Receive Disable. Set high to prevent the data at RDATA from being

sampled. Set low to allow bits at RDATA to be sampled. Should be tied

to VSS if not used. See Figure 6 for timing information. All receive side

operations are disabled when RDIS is high.

27 RCLK

I Receive Clock. Input clock from transmission link. 0 to 20 MHz. Can

be a gapped clock. Fully independent from TCLK.

28

VDD

29

VSS

30 TCLK

- Positive Supply. 3.3 volts.

- Signal Ground. 0.0 volts. Should be tied to local ground plane.

I Transmit Clock. Transmit demand clock. 0 to 20 MHz. Can be a

gapped clock. Fully independent of RCLK.

31 TDIS

I Transmit Disable. Set high to hold the current bit being transmitted at

TDATA. Set low to allow the next bit to appear at TDATA. Should be

tied to VSS if not used. See Figure 7 for timing information. All transmit

side operations are disabled when TDIS is high.

32 TDATA

O Transmit Data. Transmit NRZ serial data, updated on the rising edge of

TCLK.

DS21372 REGISTER MAP Table 2

ADDRESS R/W REGISTER NAME

00

R/W Pattern Set Register 3.

01

R/W Pattern Set Register 2.

02

R/W Pattern Set Register 1.

03

R/W Pattern Set Register 0.

04

R/W Pattern Length Register.

05

R/W Polynomial Tap Register.

06

R/W Pattern Control Register.

07

R/W Error Insert Register.

08

R Bit Counter Register 3.

09

R Bit Counter Register 2.

0A

R Bit Counter Register 1.

0B

R Bit Counter Register 0.

ADDRESS

0C

0D

0E

0F

10

11

12

13

14

15

1C

R/W

R

R

R

R

R

R

R

R

R

R/W

R/W

REGISTER NAME

Bit Error Counter Register 3.

Bit Error Counter Register 2.

Bit Error Counter Register 1.

Bit Error Counter Register 0.

Pattern Receive Register 3.

Pattern Receive Register 2.

Pattern Receive Register 1.

Pattern Receive Register 0.

Status Register.

Interrupt Mask Register.

Test Register (see note 1)

NOTE:

1. The Test Register must be set to 00 hex to insure proper operation of the DS21372.

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