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DS2154

Enhanced E1 Single Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2154 PIN DESCRIPTION Table 1-2

DS2154

TRANSMIT SIDE DIGITAL PINS

Transmit Clock [TCLK]. A 2.048 MHz primary clock. Used to clock data through the transmit side

formatter. Must be present for the parallel control port to operate properly. If not present, the Loss Of

Transmit Clock (LOTC) function can provide a clock.

Transmit Serial Data [TSER]. Transmit NRZ serial data. Sampled on the falling edge of TCLK when

the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit

side elastic store is enabled.

Transmit Channel Clock [TCHCLK]. A 256 kHz clock which pulses high during the LSB of each

channel. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with

TSYSCLK when the transmit side elastic store is enabled. Useful for parallel to serial conversion of

channel data.

Transmit Channel Block [TCHBLK]. A user-programmable output that can be forced high or low

during any of the 32 E1 channels. Synchronous with TCLK when the transmit side elastic store is

disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for

blocking clocks to a serial UART or LAPD controller in applications where not all E1 channels are used

such as Fractional E1, 384 kbps (H0), 768 kbps, 1920 kbps (H12) or ISDN-PRI. Also useful for locating

individual channels in drop-and-insert applications, for external per-channel loopback, and for per-

channel conditioning. See Section 9 for details.

Transmit System Clock [TSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the transmit

side elastic store function is enabled. Should be tied low in applications that do not use the transmit side

elastic store. Can be burst at rates up to 8.192 MHz.

Transmit Link Clock [TLCLK]. 4 kHz to 20 kHz demand clock (Sa bits) for the TLINK input. See

Section 11 for details.

Transmit Link Data [TLINK]. If enabled, this pin will be sampled on the falling edge of TCLK for data

insertion into any combination of the Sa bit positions (Sa4 to Sa8). See Section 11 for details.

Transmit Sync [TSYNC]. A pulse at this pin will establish either frame or multiframe boundaries for the

transmit side. This pin can also be programmed to output either a frame or multiframe pulse. Always

synchronous with TCLK.

Transmit Frame Sync [TSSYNC]. Only used when the transmit side elastic store is enabled. A pulse at

this pin will establish either frame or multiframe boundaries for the transmit side. Should be tied low in

applications that do not use the transmit side elastic store. Always synchronous with TSYSCLK.

Transmit Signaling Input [TSIG]. When enabled, this input will be sample signaling bits for insertion

into outgoing PCM E1 data stream. Sampled on the falling edge of TCLK when the transmit side elastic

store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is

enabled. See Section 13 for timing examples.

Transmit Elastic Store Data Output [TESO]. Updated on the rising edge of TCLK with data out of the

transmit side elastic store whether the elastic store is enabled or not. This pin is normally tied to TDATA.

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