DG421 Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

fabricante

DG421

Improved Low-Power, CMOS Analog Switches with Latches

Maxim Integrated 

Improved Low-Power,

CMOS Analog Switches with Latches

______________________________________________Timing Diagrams/Test Circuits

VOUT is the steady-state output with the switch on. Feedthrough via switch capacitance may result in spikes at the

leading and trailing edge of the output waveform.

LOGIC 3V

INPUT

0V

SWITCH 0V

OUTPUT

tR < 20ns

tF < 20ns

50%

tOFF

VOUT

0.9 x VOUT

tON

-VOUT

0.9 x VOUT

*VD = 10V for tON, VD = -10V for tOFF

NOTE: LOGIC INPUT WAVEFORM IS INVERTED FOR

SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE.

Figure 2. Switching Time

VD = 10V for tON

VD = -10V for tOFF

+5V

VL

D

IN

+15V

V+

S

RL

DG421

DG423

DG425

SWITCH OUTPUT

VOUT

CL

LOGIC

INPUT

GND

V-

-15V

( ) VOUT = VD

RL

RL + rDS(ON)

REPEAT TEST FOR IN2 AND S2.

CL INCLUDES FIXTURE AND STRAY CAPACITANCE.

3V

WR

0

3V

IN

0

3V

RS

0

SWITCH VOUT

OUTPUT 0

1.5V

tWW

tDW

2.0V

tWD

0.8V

1.5V

tRS

tOFF(RS)

0.8 x VOUT

Figure 3. Latch Timing

6 _______________________________________________________________________________________

Share Link: