CY8C3865LTI-032(2011_03) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY8C3865LTI-032
(Rev.:2011_03)

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 3: CY8C38 Family

Data Sheet

11.5.5 SWD Interface

Figure 11-72. SWD Interface Timing

(1/f_SWDCK)

SWDCK

T_SWDI_setup T_SWDI_hold

SWDIO

(PSoC 3 reading on SWDIO)

SWDIO

(PSoC 3 writing to SWDIO)

T_SWDO_valid

Table 11-76. SWD Interface AC Specifications[51]

Parameter

Description

Conditions

f_SWDCK

SWDCLK frequency

3.3 V ≤ VDDD ≤ 5 V

1.71 V ≤ VDDD < 3.3 V

1.71 V ≤ VDDD < 3.3 V,

SWD over USBIO pins

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T_SWDI_hold SWDIO input hold after SWDCK high T = 1/f_SWDCK max

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

T_SWDO_hold SWDIO output hold after SWDCK low T = 1/f_SWDCK max

11.5.6 SWV Interface

Table 11-77. SWV Interface AC Specifications[51]

Parameter

Description

SWV mode SWV bit rate

Conditions

T_SWDO_hold

Min Typ Max Units

–

–

14[52] MHz

–

–

7[52]

MHz

–

– 5.5[52] MHz

T/4

–

–

T/4

–

–

–

– 2T/5

T/4

–

–

Min

Typ Max Units

–

–

33

Mbit

Notes

51. Based on device characterization (Not production tested).

52. f_SWDCK must also be no more than 1/3 CPU clock frequency.

Document Number: 001-11729 Rev. *R

Page 111 of 129

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