Read Cycle No. 2 12 13
tRC
Address
CE
OE
Data Out
VCC
Current
High Z
ICC
ISB
tLZCE
tPU
Write Cycle No. 1 (WE Controlled)14 15 16
tACE
tLZOE
tDOE
50%
tWC
Address
tSCE
CE
WE
tAW
tSA
tPWE
OE
Data In/Out
tHZOE
Undefined
see footnotes
tSD
Data-In Valid
CY7C199C
tHZCE
tHZOE
Data Valid
High Z
tPD
50%
tHA
tHD
Notes:
12. This cycle is OE Controlled and WE is HIGH read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. This cycle is WE controlled, OE is HIGH during write.
15. Data In/Out is high impedance if OE = VIH.
16. During this period the I/Os are in output state and input signals
should not be applied.
Document #: 38-05408 Rev. *A
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