CY7C1361C-100AXC(2006) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1361C-100AXC Datasheet PDF : 31 Pages
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CY7C1361C
CY7C1363C
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
TAP Timing
1
2
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
3
4
5
6
Test Clock
(TCK)
Test Mode Select
(TMS)
tTH
tTL
tTMSS tTMSH
tCYC
tTDIS tTDIH
Test Data-In
(TDI)
tTDOV
Test Data-Out
(TDO)
tTDOX
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Parameter
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH Time
tTL
TCK Clock LOW Time
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS
TMS Set-Up to TCK Clock Rise
tTDIS
TDI Set-Up to TCK Clock Rise
tCS
Capture Set-Up to TCK Rise
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
tTDIH
TDI Hold after Clock Rise
tCH
Capture Hold after Clock Rise
Notes:
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Min.
50
20
20
0
5
5
5
5
5
5
Max.
20
10
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05541 Rev. *F
Page 14 of 31
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