CY7C1355C-133AXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1355C-133AXI
Cypress Semiconductor
CY7C1355C-133AXI Datasheet PDF : 28 Pages
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Switching Characteristics Over the Operating Range [16, 17]
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Output Times
tCDV
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Set-up Times
tAS
tALS
tWES
tCENS
tDS
tCES
Hold Times
tAH
tALH
tWEH
tCENH
tDH
tCEH
Description
VDD(Typical) to the First Access[18]
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z[19, 20, 21]
Clock to High-Z[19, 20, 21]
OE LOW to Output Valid
OE LOW to Output Low-Z[19, 20, 21]
OE HIGH to Output High-Z[19, 20, 21]
Address Set-up before CLK Rise
ADV/LD Set-up before CLK Rise
WE, BWX Set-up before CLK Rise
CEN Set-up before CLK Rise
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
Address Hold after CLK Rise
ADV/LD Hold after CLK Rise
WE, BWX Hold after CLK Rise
CEN Hold after CLK Rise
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
CY7C1355C
CY7C1357C
–133
Min. Max.
1
–100
Min. Max. Unit
1
ms
7.5
10
ns
3.0
4.0
ns
3.0
4.0
ns
6.5
7.5
ns
2.0
2.0
ns
0
0
ns
3.5
3.5
ns
3.5
3.5
ns
0
0
ns
3.5
3.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
1.5
1.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
0.5
0.5
ns
Notes:
16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a Read or Write operation
can be initiated.
19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document #: 38-05539 Rev. *E
Page 20 of 28
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