CY7C1357C-117AC Ver la hoja de datos (PDF) - Cypress Semiconductor
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fabricante
CY7C1357C-117AC
Cypress Semiconductor
CY7C1357C-117AC Datasheet PDF : 32 Pages
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PRELIMINARY
TAP Timing
Test Clock
(TCK)
Test Mode Select
(TMS)
Test Data-In
(TDI)
Test Data-Out
(TDO)
1
2
3
4
5
tTH
tTL
tTMSS tTMSH
tCYC
tTDIS tTDIH
tTDOV
tTDOX
DON’T CARE
UNDEFINED
CY7C1355C
CY7C1357C
6
TAP AC Switching Characteristics Over the operating Range[10, 11]
Parameter
Description
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
tTL
TCK Clock LOW time
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS
TMS Set-Up to TCK Clock Rise
tTDIS
TDI Set-Up to TCK Clock Rise
tCS
Capture Set-Up to TCK Rise
Hold Times
tTMSH
TMS hold after TCK Clock Rise
tTDIH
TDI Hold after Clock Rise
tCH
Capture Hold after Clock Rise
Notes:
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Min.
50
25
25
0
5
5
5
5
5
5
Max.
20
5
3.3V TAP AC Test Conditions
3.3V TAP AC Output Load Equivalent
Input pulse levels ........ ........................................VSS to 3.3V
Input rise and fall times ..................... ..............................1 ns
Input timing reference levels ...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
TDO
ZO= 50Ω
1.5V
50Ω
20pF
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #: 38-05539 Rev. **
Page 16 of 33
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