CY7C1345G(2007) Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

fabricante

CY7C1345G
(Rev.:2007)

4-Mbit (128K x 36) Flow Through Sync SRAM

Cypress Semiconductor 

CY7C1345G

Timing Diagrams (continued)

Figure 4 shows the ZZ mode timing. [19, 20]

Figure 4. ZZ Mode Timing

CLK

ZZ

I SUPPLY

A LL INPUTS

(except ZZ)

Outputs (Q)

t ZZ

t ZZI

I DDZZ

t ZZREC

High-Z

DON’T CARE

t RZZI

DESELECT or READ Only

Notes:

19. Device must be deselected when entering ZZ mode. See “Truth Table” on page 8 for all possible signal conditions to deselect the device.

20. DQs are in high-Z when exiting ZZ sleep mode.

Document Number: 38-05517 Rev. *E

Page 16 of 20

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