CY7C1345G(2007) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1345G
(Rev.:2007)

4-Mbit (128K x 36) Flow Through Sync SRAM

Cypress Semiconductor 

CY7C1345G

Timing Diagrams

Figure 1 shows the read cycle timing. [15]

Figure 1. Read Cycle Timing

CLK

ADSP

ADSC

ADDRESS

GW, BWE,BW

[A:B]

CE

ADV

OE

Data Out (Q)

tCYC

t CH t CL

tADS tADH

tADS tADH

tAS tAH

A1

A2

t WES t WEH

tCES t CEH

t

ADVS

t ADVH

Deselect Cycle

ADV suspends burst

High-Z

t OEV

t CLZ

t CDV

t OEHZ

Q(A1)

Single READ

t OELZ

tCDV

tDOH

Q(A2) Q(A2 + 1)

Q(A2 + 2)

DON’T CARE

BURST

READ

UNDEFINED

Q(A2 + 3)

Q(A2) Q(A2 + 1)

Burst wraps around

to its initial state

t CHZ

Q(A2 + 2)

Note:

15. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document Number: 38-05517 Rev. *E

Page 13 of 20

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