CY7C1325G(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor

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fabricante

CY7C1325G
(Rev.:2004)

4-Mbit (256K x 18) Flow-Through Sync SRAM

Cypress Semiconductor 

Timing Diagrams (continued)

Read/Write Timing[16, 18, 19]

tCYC

CLK

ADSP

t

CH

tCL

tADS tADH

ADSC

ADDRESS A1

tAS tAH

A2

BWE, BW[A:B]

CE

tCES tCEH

PRELIMINARY

A3

A4

t

WES

tWEH

CY7C1325G

A5

A6

ADV

OE

Data In (D)

Data Out (Q)

High-Z

t

OEHZ

Q(A1)

Q(A2)

Back-to-Back READs

tDS tDH

D(A3)

Single WRITE

tOELZ

tCDV

Q(A4)

Q(A4+1) Q(A4+2)

BURST READ

DON’T CARE

UNDEFINED

Notes:

18. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

19. GW is HIGH.

Q(A4+3)

D(A5)

D(A6)

Back-to-Back

WRITEs

Document #: 38-05518 Rev. *A

Page 12 of 16

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