CY14B101Q1A-SF104XI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B101Q1A-SF104XI Datasheet PDF : 34 Pages
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CY14C101Q
CY14B101Q, CY14E101Q
Write Protection and Block Protection
CY14X101Q provides features for both software and hardware
write protection using WRDI instruction and WP. Additionally, this
device also provides block protection mechanism through BP0
and BP1 pins of the Status Register.
The write enable and disable status of the device is indicated by
WEN bit of the Status Register. The write instructions (WRSR,
WRITE and WRSN) and nvSRAM special instruction (STORE,
RECALL, ASENB and ASDISB) need the write to be enabled
(WEN bit = ‘1’) before they can be issued.
Write Enable (WREN) Instruction
On power-up, the device is always in the write disable state. The
following WRITE, WRSR, WRSN, or nvSRAM special instruction
must therefore be preceded by a Write Enable instruction. If the
device is not write enabled (WEN = ‘0’), it ignores the write
instructions and returns to the standby state when CS is brought
HIGH. A new CS falling edge is required to re-initiate serial
communication. The instruction is issued following the falling
edge of CS. When this instruction is used, the WEN bit of Status
Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up.
Note After completion of a write instruction (WRSR, WRITE and
WRSN) or nvSRAM special instruction (STORE, RECALL,
ASENB, and ASDISB) instruction, WEN bit is cleared to ‘0’. This
is done to provide protection from any inadvertent writes.
Therefore, WREN instruction needs to be used before a new
write instruction is issued.
Figure 10. WREN Instruction
CS
SCK
01 234567
SI
00000110
SO
HI-Z
Write Disable (WRDI) Instruction
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following the falling edge of CS followed
by opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 11. WRDI Instruction
CS
SCK
01 234567
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 5 shows the function of
Block Protect bits.
Table 5. Block Write Protect Bits
Level
0
1 (1/4)
2 (1/2)
3 (All)
Status Register
Bits
BP1 BP0
0
0
0
1
1
0
1
1
Array Addresses Protected
None
0x18000-0x1FFFF
0x10000-0x1FFFF
0x00000-0x1FFFF
Hardware Write Protection (WP)
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This allows you to install the device in a system
with the WP pin tied to ground, and still write to the Status
Register.
WP pin can be used along with WPEN and Block Protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to the Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
Note CY14X101Q2A does not have WP pin and therefore does
not provide hardware write protection.
Table 6 summarizes all the protection features of this device
Table 6. Write Protection Operation
WPEN
WP
WEN
Protected
Blocks
Unprotected
Blocks
X
X
0 Protected Protected
0
X
1 Protected Writable
1 LOW 1 Protected Writable
1 HIGH 1 Protected Writable
Status
Register
Protected
Writable
Protected
Writable
SI
00000100
SO
HI-Z
Document #: 001-54393 Rev. *F
Page 12 of 34
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