CY14B101I Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B101I Datasheet PDF : 42 Pages
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PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
Memory Slave Device
The nvSRAM device is selected for read/write if the master
issues the slave address as 1010b followed by two bits of device
select. If slave address sent by the master matches with the
Memory Slave device address then depending on the R/W bit of
the slave address, data will be either read from (R/W = ‘1’) or
written to (R/W = ‘0’) the nvSRAM.
The address length for CY14X101I is 17 bits, and thus it requires
three address bytes to map the entire memory address location.
To save an extra byte for memory addressing, the 17th bit (A16)
is mapped to the slave address select bit (A0). The dedicated
two address bytes represent bit A0 to A15.
Figure 7. Memory Slave Device Address
handbook, halfpMagSe B
10
LSB
1 0 A2 A1 A16 R/W
Slave ID
Device MSB of
Select Address
RTC Registers Slave Device
The RTC Registers is selected for read/write if the master issues
the slave address as 1101b followed by two bits of device select.
Then, depending on the R/W bit of the slave address, data is
either read from (R/W = ‘1’) or written to (R/W = ‘0’) the RTC
Registers. The RTC Registers slave address is followed by one
byte address of RTC Register for read/write operation. The RTC
Registers map is explained in the Table 11.
Figure 8. RTC Registers Slave Device Address
handbook, halfpMagSe B
LSB
1 1 0 1 A2 A1 X R/W
Slave ID
Device
Select
Control Registers Slave Device
The Control Registers Slave device includes the serial number,
product ID, Memory Control, and Command Register.
The nvSRAM Control Register Slave device is selected for
read/write if the master issues the slave address as 0011b
followed by two bits of device select. Then, depending on the
R/W bit of the slave address, data is either read from (R/W = ‘1’)
or written to (R/W = ‘0’) the device.
Figure 9. Control Registers Slave Device Address
handbook, halfpMagSe B
00
LSB
1 1 A2 A1 X R/W
Slave ID
Device
Select
Table 3. Control Registers Map
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0xAA
Description
Memory
Control
Register
Serial Number
8 bytes
Device ID
Reserved
Command
Register
Read/Write
Details
Read/Write Contains Block
Protect bits and Serial
Number lock bit
Read/Write Programmable Serial
(Read only Number. Locked by
when SNL setting the Serial
is set) Number lock bit in the
Memory Control
Register to ‘1’.
Read only Device ID is factory
programmed
Reserved
Write only
Reserved
Allows commands for
STORE, RECALL,
AutoStore
Enable/Disable,
SLEEP Mode
Memory Control Register
The Memory Control Register contains the following bits:
Table 4. Memory Control Register Bits
Bit 7
0
Bit 6
SNL
(0)
Bit 5
0
Bit 4
0
Bit 3
BP1
(0)
Bit 2
BP0
(0)
Bit 1
0
Bit 0
0
■ BP1:BP0: Block protect bits are used to protect 1/4, 1/2 or full
memory array. These bits can be written through a write
instruction to the 0x00 location of the Control Register Slave
device. However, any STORE cycle transfers SRAM data into
a nonvolatile cell regardless of whether or not the block is
protected. The default value shipped from the factory for BP0
and BP1 is ‘0’.
Table 5. Block Protection
Level
0
1/4
1/2
1
BP1:BP0
00
01
10
11
Block Protection
None
0x18000-0x1FFFF
0x10000-0x1FFFF
0x00000-0x1FFFF
■ SNL (S/N Lock) Bit: Serial Number Lock bit (SNL) is used to
lock the serial number. Once the bit is set to ‘1’, the serial
number registers are locked and no modification is allowed.
This bit cannot be cleared to ‘0’. The serial number is secured
on the next STORE operation (Software STORE or AutoStore).
If AutoStore is not enabled, user must perform Software
STORE operation to secure the lock bit status. If a STORE was
not performed, the serial number lock bit will not survive power
cycle. The default value shipped from the factory for SNL is ‘0’.
Document #: 001-54391 Rev. *C
Page 8 of 42
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