CY14B101I Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY14B101I Datasheet PDF : 42 Pages
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PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
Current Control Registers Read
A read of Control Registers Slave is started with master sending the Control Registers Slave address after the START condition with
the LSB set to ‘1’. The reads begin from the current address which is the next address to the last accessed location. The reads to
Control Registers Slave continues until the last readable address location and loops back to the first location (0x00). Note that the
Command Register is a write only register and is not accessible through the sequential read operations. If a burst read operation
begins from the Command Register (0xAA), the address counter wraps around to the first address in the register map (0x00).
Figure 31. Control Registers Single-Byte Read
By Master
SDA Line
By nvSRAM
S
T
A
Control Registers
R
Slave Address
T
S 0 0 1 1 A2 A1 X 1
A
Data Byte
S
A
T
0
P
P
Figure 32. Current Control Registers Multi-Byte Read
By Master
SDA Line
By nvSRAM
S
T
A
Control Registers
R
Slave Address
T
S 0 0 1 1 A2 A1 X 1
A
A
Data Byte
Data Byte N
S
AT
0
P
P
Random Control Registers Read
A read of random address may be performed by initiating a write operation to the intended location of read and immediately following
with a Repeated START operation. The reads to Control Registers Slave continues till the last readable address location and loops
back to the first location (0x00). Note that the Command Register is a write only register and is not accessible through the sequential
read operations. A random read starting at the Command Register (0xAA) loops back to the first address in the Control Register
register map (0x00). If a random read operation is initiated from an out-of-bound memory address, the nvSRAM sends a NACK after
the address byte is sent.
Figure 33. Random Control Registers Single-Byte Read
By Master
SDA Line
By nvSRAM
S
T
A
Control Registers
R
Slave Address
T
S 0 0 1 1 A2 A1 X 0
Control Register Address
A
Control Registers Slave Address
Sr 0 0 1 1 A2 A1 X 1
A
A
Data Byte
S
T
A0
P
P
Document #: 001-54391 Rev. *C
Page 18 of 42
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