CS5463 Ver la hoja de datos (PDF) - Cirrus Logic
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CS5463 Datasheet PDF : 46 Pages
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CS5463
5.16.5 Register Read/Write
B7 B6 B5 B4 B3 B2 B1 B0
0 W/R RA4 RA3 RA2 RA1 RA0 0
The Read/Write informs the command decoder that a register access is required. During a read operation, the ad-
dressed register is loaded into an output buffer and clocked out by SCLK. During a write operation, the data is
clocked into an input buffer and transferred to the addressed register upon completion of the 24th SCLK.
W/R
Write/Read control
0 = Read
1 = Write
RA[4:0]
Register address bits (bits 5 through 1) of the read/write command.
Register Page 0
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RA[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Name
Config
IDCoff
Ign
VDCoff
Vgn
Cycle Count
PulseRateE
I
V
P
PActive
IRMS
εVRMS
(Epsilon)
Poff
Status
IACoff
VACoff
Mode
T
QAVG
Q
IPeak
VPeak
QTrig
PF
Mask
S
Ctrl
PH
PF
QF
Description
Configuration
Current DC Offset
Current Gain
Voltage DC Offset
Voltage Gain
Number of A/D conversions used in one computation cycle (N)).
Sets the E1, E2 and E3 energy-to-frequency output pulse rate.
Instantaneous Current
Instantaneous Voltage
Instantaneous Power
Active (Real) Power
RMS Current
RMS Voltage
Ratio of line frequency to output word rate (OWR)
Power Offset
Status
Current AC (RMS) Offset
Voltage AC (RMS) Offset
Operation Mode
Temperature
Average Reactive Power
Instantaneous Reactive Power
Peak Current
Peak Voltage
Reactive Power calculated from Power Triangle
Power Factor
Interrupt Mask
Apparent Power
Control
Harmonic Active Power
Fundamental Active Power
Fundamental Reactive Power / Page
Note: For proper operation, do not attempt to write to unspecified registers.
24
DS678F2
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