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MAX3890ECB

+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs

Maxim Integrated 

+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer

with Clock Synthesis and LVDS Inputs

VCC

50Ω

50Ω

SLBO+

ESD

STRUCTURE

SLBO-

VCC

50Ω 50Ω

SLBI+

SLBI-

GND

OUTPUT CIRCUIT

Figure 3. Current-Mode Logic

INPUT CIRCUIT

Applications Information

Alternative PECL-Output Termination

Figure 4 shows alternative PECL-output termination

methods. Use Thevenin-equivalent termination when a

(VCC - 2V) termination voltage is not available. If AC-

coupling is necessary, be sure that the coupling capac-

itor is placed following the 50Ω or Thevenin-equivalent

DC termination.

Layout Techniques

For best performance, use good high-frequency layout

techniques. Filter voltage supplies and keep ground

connections short. Use multiple vias where possible.

Also, use controlled-impedance transmission lines to

interface with the MAX3890 clock and data inputs and

outputs.

Exposed Pad (EP) Package

The EP 64-pin TQFP incorporates features that provide

a very low thermal resistance path for heat removal

from the IC to a PC board. The MAX3890’s exposed

pad must be soldered directly to a ground plane with

good thermal conductance.

MAX3890

SCLKO+

OR SDO+

SCLKO-

OR SDO-

+3.3V

130Ω

130Ω

Z0 = 50Ω

Z0 = 50Ω

82Ω

PECL

INPUTS

82Ω

MAX3890

SCLKO+

OR SDO+

Z0 = 50Ω

SCLKO-

OR SDO-

Z0 = 50Ω

50Ω

50Ω

VCC - 2V

Figure 4. Alternative PECL-Output Termination

HIGH-

IMPEDANCE

INPUTS

8 _______________________________________________________________________________________

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