CAT5241WI-00-T1 Ver la hoja de datos (PDF) - ON Semiconductor
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CAT5241WI-00-T1
ON Semiconductor
CAT5241WI-00-T1 Datasheet PDF : 16 Pages
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CAT5241
Quad Digitally Programmable Potentiometer (DPP™) with
64 Taps and I²C Interface
FEATURES
Four linear-taper digitally programmable
potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5 kΩ, 10 kΩ, 50 kΩ or
100 kΩ
Potentiometer control and memory access via
I²C interface
Low wiper resistance, typically 80 Ω
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1 µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
20-lead SOIC and TSSOP packages
Industrial temperature range
For Ordering Information details, see page 15.
DESCRIPTION
The CAT5241 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a I²C serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register (WCR).
The CAT5241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC 20 Lead (W)
TSSOP 20 Lead (Y)
RW0 1
20 VCC
RL0 2
19 RW3
RH0 3
18 RL3
A0 4
17 RH3
A2 5 CAT 16 A1
RW1 6 5241 15 A3
RL1 7
14 SCL
RH1 8
13 RW2
SDA 9
12 RL2
GND 10
11 RH2
SCL
SDA
A0
A1
A2
A3
FUNCTIONAL DIAGRAM
RH0 RH1 RH2 RH3
I2C BUS
INTERFACE
CONTROL
LOGIC
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2 RL3
RW0
RW1
RW2
RW3
© 2009 SCILLC. All rights reserved.
1
Characteristics subject to change without notice
Doc. No. MD-2011 Rev. R
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