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CA3310

CMOS, 10-Bit, A/D Converters with Internal Track and Hold

Intersil 

CA3310, CA3310A

Single +5V Supply

If only a single +5V supply is available, an ICL7660 can be

used to provide approximately +8V and -4V to the opera-

tional amplifier. Figure 20 shows this approach. Note that the

converter and associated capacitors should be grounded to

the digital supply. The 1kΩ in series with each supply at the

operational amplifier isolates digital and analog grounds.

+5V

10Ω

+

8

2

ICL7660S 4

5

D

+

+

IN914

+8V

+

D

- 4V

3

+ ALL CAPACITORS - 10µF, 10V

D

D

D = DIGITAL GROUND

Digital Sample and Hold

With a minimum of external logic, the CA3310 can be made

to wait at the verge of ending a sample. A start pulse will then,

after the internal aperture delay, capture the input and finish

the conversion cycle. Figure 21 illustrates this application.

The CA3310 is connected as if to free run. The Data Ready

signal is shifted through a CD74HC175, and at the low-going

clock edge just before the sample would end, is used to hold

the clock low.

The same signal, active high, is available to indicate the

CA3310 is ready to convert. A low pulse to reset the

CD74HC175 will now release the clock, and the sample will

end as it goes positive. Ten cycles later, the conversion will

be complete, and DRDY will go active.

Operating and Handling Considerations

HANDLING

All inputs and outputs of Intersil CMOS devices have a

network for electrostatic protection during handling. Recom-

mended handling practices for CMOS devices are described

in lCAN-6526, “Guide to Better Handling and Operation of

CMOS Integrated Circuits”.

OPERATING

Operating Voltage

During operation near the maximum supply voltage limit,

care should be taken to avoid or suppress power supply

turn-on and turn-off transients, power supply ripple, or

ground noise; any of these conditions must not cause

VDD - VSS to exceed the absolute maximum rating.

Input Signals

To prevent damage to the input protection circuit, input

signals should never be greater than VDD +0.3V nor less

than VSS -0.3V. Input currents must not exceed 20mA even

when the power supply is off.

Unused Inputs

A connection must be provided at every input terminal. All

unused Input terminals must be connected to either VDD or

VSS, whichever is appropriate.

Output Short Circuits

Shorting of outputs to VDD or VSS may damage CMOS

devices by exceeding the maximum device dissipation.

+5V

D

FULL SCALE

REFERENCE

ANALOG

INPUT

INPUT BUFFED

AS REQUIRED

CA3310/A

VDD

VAA +

A

VREF +

DRST

STRT

D0 - D9

OEL

A

VIN

VREF -

VAA -

A

VSS

OEM

DRDY

REXT

CLK

+5V

D

DATA TO SYSTEM

OUTPUT ENABLES

DATA READY

IN914

D

KEEP CAPACITANCE AT REXT/CLK NODE

AS LOW AS POSSIBLE

D = DIGITAL GROUND

A = ANALOG GROUND

1/16

CD74HCO4E

D0 Q0

CP

D1 Q1 D2

CD74HC175E

Q2 Q2

VDD

GND

D3 Q0 Q1 Q3 Q3 MR

D

NC

FIGURE 20. DIGITAL TRACK-AND-HOLD BLOCK DIAGRAM

READY TO

CONVERT

+5V

D

START

CONVERT

6-19

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