C8051F366 Ver la hoja de datos (PDF) - Silicon Laboratories

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C8051F366

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

DOCUMENT CHANGE LIST

Revision 0.1 to Revision 0.2

• Updated specification tables with most recently available characterization data.

• Fixed an error with the SYSCLK specification in Table 3.1, “Global Electrical Characteristics,” on

page 33.

• Corrected the name of the PMAT bit in SFR Definition 10.2. IP: Interrupt Priority.

• Corrected the reset value for SFR Definition 22.2. PCA0MD: PCA0 Mode.

Revision 0.2 to Revision 1.0

• Updated specification tables with characterization data.

• Fixed Table 1.1, “Product Selection Guide,” on page 19 to reflect the correct number of Port I/O pins

for the C8051F361/2/4/5.

• Updated Section “10. Interrupt Handler” on page 107.

- Added note describing EA change behavior when followed by single cycle instruction.

• Updated SFR Definition 11.1

- Changed the MAC0SC (MAC0CF.5) bit description to correctly refer to the MAC0SD bit.

• Updated SFR Definition 15.2.

- Changed the EMI0CF description to properly describe the 1k XRAM boundaries.

• Added Table 16.2, “Internal Low Frequency Oscillator Electrical Characteristics,” on page 172.

• Updated SFR Definition 16.9:

- Specified that the undefined states for PLLLP3–0 are RESERVED.

• Added Table 19.7 and Table 19.8 on page 233 for UART Baud Rates when using the PLL.

• Updated Table 22.1, “PCA Timebase Input Options,” on page 265:

- Specified that the undefined states of CPS2–0 are RESERVED.

• Added Revision B to “Revision Specific Behavior” on page 281.

Rev. 1.0

287

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