C8051F300 Ver la hoja de datos (PDF) - Silicon Laboratories
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C8051F300 Datasheet PDF : 177 Pages
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C8051F300/1/2/3/4/5
VDD
Analog/Digital
Power
GND
/RST/C2CK
XTAL1
XTAL2
8
C2D
Debug HW
0
8kbyte
5 Reset
FLASH
POR
Brown-
Out
1
256 byte
SRAM
External
Oscillator
Circuit
C
o SFR Bus
r System Clock
Precision
e
Internal
Oscillator
Clock & Reset
Configuration
Port I/O Mode
& Config.
Port 0
Latch
x2
UART
Timer 0, 1
P
X
0
B
A
D
PCA/
x4
R
r
WDT
v
x2
SMBus
CP0
XBAR
Control
C2D
ADC
Config. &
Control
CNVSTR
CP0
+
-
VDD
VREF
Temp
8-bit
500ksps
ADC
A
M
PGA
U
X
VDD
AIN0-AIN7
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7/C2D
Figure 1.1. C8051F300/2 Block Diagram
VDD
Analog/Digital
Power
GND
/RST/C2CK
XTAL1
XTAL2
8
C2D
Debug HW
0
8k/4k/2k
byte
5 Reset
FLASH
POR
Brown-
Out
1
256 byte
SRAM
C
External
Oscillator
Circuit
o SFR Bus
r System Clock
Precision
e
Internal
Oscillator
Clock & Reset
Configuration
Port I/O Mode
& Config.
Port 0
Latch
x2
UART
Timer 0, 1
PCA/
x4
WDT
x2
SMBus
CP0
XBAR
Control
P
X
0
B
A
D
R
r
v
C2D
CP0
+
-
Figure 1.2. C8051F301/3/4/5 Block Diagram
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6
P0.7/C2D
Rev. 2.9
15
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