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74LV161

Presettable synchronous 4-bit binary counter; asynchronous reset

Philips Electronics 

Philips Semiconductors

Presettable synchronous 4-bit binary counter;

asynchronous reset

Product specification

74LV161

FEATURES

• Optimized for low voltage applications: 1.0 to 3.6 V

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,

Tamb = 25°C

• Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,

Tamb = 25°C

• Asynchronous reset

• Synchronous counting and loading

• Two count enable inputs for n-bit cascading

• Positive-edge triggered clock

• Output capability: standard

• ICC category: MSI

DESCRIPTION

The 74LV161 is a low-voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT161.

The 74LV161 is a synchronous presettable binary counter which

features an internal look-head carry and can be used for high-speed

counting. Synchronous operation is provided by having all flip-flops

clocked simultaneously on the positive-going edge of the clock (CP).

The outputs (Q0 to Q3) of the counters may be preset to a HIGH or

LOW level. A LOW level at the parallel enable input (PE) disables the

counting action and causes the data at the data inputs (D0 to D3) to be

loaded into the counter on the positive-going edge of the clock

(providing that the set-up and hold time requirements for PE are met).

Preset takes place regardless of the levels at count enable inputs

(CEP and CET). A low level at the master reset input (MR) sets all

four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the

levels at CP, PE, CET and CEP inputs (thus providing an

asynchronous clear function).

The look-ahead carry simplifies serial cascading of the counters.

Both count enable inputs (CEP and CET) must be HIGH to count.

The CET input is fed forward to enable the terminal count output

(TC). The TC output thus enabled will produce a HIGH output pulse

of a duration approximately equal to a HIGH level output of Q0. This

pulse can be used to enable the next cascading stage. The

maximum clock frequency for the cascaded counters is determined

by the CP to TC propagation delay and CEP to CP set-up time,

according to the following formula:

fmax + tp(max)

(CP

to

1

TC) ) tsu(CEP

to

CP)

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns

SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH

Propagation delay

CP to Qn

CP to TC

MR to Qn

MR to TC

CET to TC

CL = 15 pF;

VCC = 3.3 V

fmax

Maximum clock frequency

CI

Input capacitance

CPD

Power dissipation capacitance per gate

VI = GND to VCC1

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD VCC2 fi )ȍ (CL VCC2 fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

ȍ (CL VCC2 fo) = sum of the outputs.

TYPICAL

15

18

15

17

9

77

3.5

25

UNIT

ns

MHz

pF

pF

ORDERING INFORMATION

PACKAGES

16-Pin Plastic DIL

16-Pin Plastic SO

16-Pin Plastic SSOP Type II

16-Pin Plastic TSSOP Type I

TEMPERATURE RANGE OUTSIDE NORTH AMERICA

–40°C to +125°C

74LV161 N

–40°C to +125°C

74LV161 D

–40°C to +125°C

74LV161 DB

–40°C to +125°C

74LV161 PW

NORTH AMERICA

74LV161 N

74LV161 D

74LV161 DB

74LV161PW DH

PKG. DWG. #

SOT38-4

SOT109-1

SOT338-1

SOT403-1

1997 May 15

2

853–1917 18039

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