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74LV161

Presettable synchronous 4-bit binary counter; asynchronous reset

Philips Electronics 

Philips Semiconductors

Presettable synchronous 4-bit binary counter;

asynchronous reset

Product specification

74LV161

VI

CEP, CET

INPUT

VM

GND

tsu

tsu

th

VI

CP INPUT

VM

GND

The shaded areas indicate when the input is permitted to change

for predictable output performance.

th

SV00580

Figure 5. CEP and CET set-up and hold times.

TEST CIRCUIT

VCC

PULSE

GENERATOR

VI

RT

VO

D.U.T.

CL

S1

2 x VCC

Open

GND

RL

RL

Test Circuit for switching times

SWITCH POSITION

TEST

S1

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

2 x VCC

GND

VCC

< 2.7V

2.7–3.6V

VI

VCC

2.7V

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

CL = Load capacitance includes jig and probe capacitance:

See AC CHARACTERISTICS for value.

RT = Termination resistance should be equal to ZOUT of

pulse generators.

SV00776

Figure 6. Load circuitry for switching times.

1997 May 15

10

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