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SAA5665

Enhanced TV microcontrollers with On-Screen Display (OSD)

Philips Electronics 

Philips Semiconductors

Enhanced TV microcontrollers with

On-Screen Display (OSD)

Product specification

SAA56xx

8.3 RAM organisation

Figure 6 shows the internal Data RAM is organised into

two areas: Data memory and the Special Function

Registers (SFRs).

8.4 Data memory

The Data memory (see Fig.6) is 256 × 8 bits and occupies

address range 00H to FFH when using indirect addressing

and 00H to 7FH when using direct addressing. The SFRs

occupy the address range 80H to FFH and are accessible

using direct addressing only.

The lower 128 bytes of Data memory are mapped as

shown in Fig.7. The lowest 32 bytes are grouped into four

banks of eight registers selectable via SFR PSW

bits <4:3> (RS1/RS0; see Table 3), the next 16 bytes

above the register banks form a block of bit addressable

memory space.

The upper 128 bytes are not allocated for any special area

or functions.

Table 3 Bank selection

RS1

RS0

0

0

0

1

1

0

1

1

BANK

Bank 0

Bank 1

Bank 2

Bank 3

handbook, halfpage

7FH

handbook, halfpage

DATA

MEMORY

FFH

upper 128 bytes

80H

7FH

lower 128 bytes

00H

accessible

by indirect

addressing

only

accessible

by direct

and indirect

addressing

SPECIAL

FUNCTION

REGISTERS

accessible

by direct

addressing

only

MBK956

Fig.6 Internal Data memory.

2FH

bank select

bits in PSW

20H

1FH

11 = BANK 3

18H

17H

10 = BANK 2

10H

0FH

01 = BANK 1

08H

07H

00 = BANK 0

00H

bit-addressable

space

(bit addresses

00H to 7FH)

4 banks of

8 registers

(R0 to R7)

GSA060

Fig.7 Lower 128 bytes of internal RAM.

2001 Dec 13

12

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