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BD8961NV-E2

Low Noise High Efficiency Step-down Switching Regulator with Built-in Power MOSFET

ROHM Semiconductor 

BD8961NV

Technical Note

●Switching regulator efficiency

Efficiency ŋ may be expressed by the equation shown below:

η= VOUT×IOUT ×100[%]= POUT ×100[%]=

Vin×Iin

Pin

POUT

POUT+PDα

×100[%]

Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:

Dissipation factors:

1) ON resistance dissipation of inductor and FET：PD(I2R)

2) Gate charge/discharge dissipation：PD(Gate)

3) Switching dissipation：PD(SW)

4) ESR dissipation of capacitor：PD(ESR)

5) Operating current dissipation of IC：PD(IC)

1)PD(I2R)=IOUT2×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output

current.)

2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[Hz]：Switching frequency, V[V]：Gate driving voltage of FET)

3)PD(SW)=

Vin2×CRSS×IOUT×f

IDRIVE

(CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.)

4)PD(ESR)=IRMS2×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.)

5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)

●Consideration on permissible dissipation and heat generation

As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is

needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input

voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation

must be carefully considered.

For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.

Because the conduction losses are considered to play the leading role among other dissipation mentioned above including

gate charge/discharge dissipation and switching dissipation.

①3.9W

4.0

3.0

2.0

①for SON008V5060

JEDEC 4 layer board 76.2×114.3×1.6mm

θj-a=32.1℃/W

②for SON008V5060

ROHM standard 1 layer board 70×70×1.6mm

θj-a=138.9℃/W

③ IC only

θj-a=195.3℃/W

P=IOUT2×RON

RON=D×RONP+(1-D)RONN

D：ON duty (=VOUT/VCC)

RCOIL：DC resistance of coil

RONP：ON resistance of P-channel MOS FET

RONN：ON resistance of N-channel MOS FET

IOUT：Output current

1.0 ②0.90W

③0.64W

0

0 25 50 75 100105 125 150

Ambient temperature:Ta [℃]

Fig.25 Thermal derating curve

(SON008V5060)

If VCC=5V, VOUT=3.3V, RONP=0.2Ω, RONN=0.16Ω

IOUT=2A, for example,

D=VOUT/VCC=3.3/5.0=0.66

RON=0.66×0.20+(1-0.66)×0.16

=0.132+0.0544

=0.1864[Ω]

P=22×0.1864＝0.7456W]

As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater.

With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.

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8/13

2010.04 - Rev.B

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