AT24C04A(2004) Ver la hoja de datos (PDF) - Atmel Corporation

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AT24C04A
(Rev.:2004)

Two-wire Serial EEPROM Extended Temperature

Atmel Corporation 

Figure 4. Bus Timing

AT24C02A/04A/08A/16A

MEMORY RESET: After an interruption in protocol, power loss or system reset, any

two-wire part can be reset by following these steps:

1. Clock up to 9 cycles.

2. Look for SDA high in each cycle while SCL is high.

3. Create a start condition as SDA is high.

Figure 5. Write Cycle Timing

SCL

SDA

8th BIT

ACK

Note:

WORDn

(1)

twr

STOP

CONDITION

START

CONDITION

The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the interval clear/write cycle.

7

5083A–SEEPR–9/04

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