AT17C010A Ver la hoja de datos (PDF) - Atmel Corporation

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AT17C010A

FPGA Configuration EEPROM Memory

Atmel Corporation 

Block Diagram

SER_EN

WP1

OSC

CONTROL

OSC

POWER ON

RESET

PROGRAMMING

MODE LOGIC

ROW

ADDRESS

COUNTER

BIT

COUNTER

AT17C/LV512A/010A

PROGRAMMING

DATA SHIFT

REGISTER

ROW

DECODER

TC

EEPROM

CELL

MATRIX

COLUMN

DECODER

DCLK READY

OE

(Optional)

nCS nCASC (A2)

DATA

Device Configuration

The control signals for the configuration EEPROM (nCS, OE and DCLK) interface

directly with the FPGA device control signals. All FPGA devices can control the entire

configuration process and retrieve data from the configuration EEPROM without requir-

ing an external intelligent controller.

The configuration EEPROM’s OE and nCS pins control the tri-state buffer on the DATA

output pin and enable the address counter and the oscillator. When OE is driven Low,

the configuration EEPROM resets its address counter and tri-states its DATA pin. The

nCS pin also controls the output of the AT17A Series Configurator. If nCS is held High

after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.

When nCS is driven Low, the counter and the DATA output pin are enabled. When OE

is driven Low again, the address counter is reset and the DATA output pin is tri-stated,

regardless of the state of the nCS.

When the Configurator has driven out all of its data and nCASC is driven Low, the

device tri-states the DATA pin to avoid contention with other Configurators. Upon

power-up, the address counter is automatically reset.

3

0974E–08/01

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