TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . Figure 1a Unless Otherwise Noted
TAG RAM READ CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
Max
Unit
Clock Access Time
tKHQV
—
Output Enable to Output Valid
tGLQV
—
Output Enable to Output Active
tGLQX
0
Output Disable to Q High–Z
tGHQZ
1
Status Bit Hold from Address Change
tAXSX
3
Address Access Time Status Bits
tAVSV
—
Tag Bit Hold from Address Change
tAVQX
3
Address Access Time Tag Bits
tAVQV
—
NOTES:
1. Setup and hold times, W (write) refers to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag reads are asynchronous.
10
ns
8
ns
—
ns
6
ns
—
ns
10
ns
—
ns
12
ns
TAG RAM WRITE CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
Max
Unit
Cycle Time
tKHKH
15
—
ns
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output Active
tKHKL
4.5
tKLKH
4.5
tKHQX
1.5
—
ns
—
ns
—
ns
Setup Times
Address
tAVKH
3
Write
tWVKH
—
ns
Hold Times
Address
tKHAX
1.5
Write
tKHWX
—
ns
Status Output Hold
tKHSX
0
—
ns
Clock High to Status Bits Valid
tKHSV
—
NOTES:
1. Setup and hold times, W (write) refers to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag writes are synchronous.
9
ns
MOTOROLA FAST SRAM
MPC2104P•MPC2105P
11