AGM2416B Ver la hoja de datos (PDF) - AZ Displays
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AGM2416B Datasheet PDF : 12 Pages
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AZ DISPLAYS, INC.
AGM2412B
20
V34R
Normally use the bias voltages set by a resistor divider
Ensure that voltages are set such that VSS • • V5 < V43 < V12 < V0.
21
V12R
ViL and ViR (i = 0,12, 43, 5) must connect to an external power supply, and
22
V0R supply regular voltage which is assigned by specification for each power pin
Common Pin
Pin No. Symbol
23
V0L
24
V12L
25
V34L
26
VSS
27
VSS
28
VSS
29
VDD
30
VDD
31
VDD
32
EIO2
33
D7
34
DOFFB
35
LP
36
FR
37
V34R
38
V12R
39
V0R
Function Description
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider.
Ensure that voltages are set such that VSS < V43 < V12 < V0.
ViL and ViR (i = 0,12, 43) must connect to an external power supply, and
supply regular voltage that is assigned by specification for each power pin.
Ground
Logic power supply
Shift data input for shift register at common mode
Dual mode data input at common mode
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
When set to VSS level "L", the LCD drive output pins (Y1-Y160) are set to level
Vss.
When set to "L¡±, the contents of the shift register are reset to not reading
data. When the /DISPOFF function is canceled, the driver outputs non-select
level (V12 or V43), and the shift data is read at the next falling edge of the LP. At
that time, if /DISPOFF removal time does not correspond to what is shown in
AC characteristics, the shift data is not read correctly.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Shift clock pulse input pin for bi-directional shift register
* Data is shifted at the falling edge of the clock pulse.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the shift
register output signal and the FR signal.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider.
Ensure that voltages are set such that VSS < V43 < V12 < V0.
ViL and ViR (i = 0,12, 43) must connect to an external power supply, and
supply regular voltage that is assigned by specification for each power pin.
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