ADT7490 Ver la hoja de datos (PDF) - Analog Devices
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ADT7490 Datasheet PDF : 76 Pages
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TEMPERATURE MEASUREMENT
The ADT7490 has four temperature measurement channels:
one local, two remote thermal diodes, and a PECI. The local
and thermal diode readings are analog temperature measure-
ments, whereas PECI is a digital temperature reading.
PECI Temperature Measurement
The PECI interface is a dedicated thermal interface. The CPU
temperature measurement is carried out internally in the CPU.
This information is digitized and transferred to the ADT7490
via the PECI interface. The ADT7490 is a PECI host device and
therefore, polls the CPU for thermal information.
The PECI measurement differs from traditional thermal diode
temperature measurements in that the measurement is a relative
value instead of an absolute value. The PECI reading is a nega-
tive value that indicates how close the CPU temperature is from
the thermal throttling or TCC point of the CPU.
The ADT7490 records and uses the PECI measurement for fan
control in its relative format. Therefore, care must be taken in
programming the relevant limits and fan control parameters in
the PECI format. Refer to the PECI Input section and Table 6
for further PECI information.
PECI monitoring is enabled on the ADT7490 by setting the
PECI monitoring bit in Configuration Register 1 (Register 0x40,
Bit 4). The ADT7490 can measure the temperature of up to
four dual-core CPUs. The number of CPUs in the system that
provide PECI information is set in Bits [7:6] of Register 0x88.
Each CPU is distinguished by the PECI address. The number
of domains, or domain count, per CPU address must also be
programmed into the ADT7490. The ADT7490 reads the
temperature of both domains per CPU, however, only the PECI
value of the hottest domain is recorded in the PECI value
register.
PECI0 domains: Register 0x36, Bit 3
PECI1 domains: Register 0x88, Bit 5
PECI2 domains: Register 0x88, Bit 4
PECI3 domains: Register 0x88, Bit 3
PECI Reading Registers
Register 0x33, PECI0: PECI reading from CPU Address 0x30
Register 0x1A, PECI1: PECI reading from CPU Address 0x31
Register 0x1B, PECI2: PECI reading from CPU Address 0x32
Register 0x1C, PECI3: PECI reading from CPU Address 0x33
PECI Limit Registers
Each PECI measurement shares the same high and low limits.
Register 0x34, PECI Low Limit = 0x81 default
Register 0x35, PECI High Limit = 0x00 default
ADT7490
PECI Offset Registers
Each PECI reading has a dedicated offset register to calibrate
the PECI measurement and account for errors in the tempera-
ture reading. The LSBs add a 1°C offset to the temperature
reading so that the 8-bit register effectively allows temperature
offsets of up to ±128°C with a resolution of 1°C.
Register 0x94, PECI0 Offset
Register 0x95, PECI1 Offset
Register 0x96, PECI2 Offset
Register 0x97, PECI3 Offset
PECI Data Smoothing
The PECI smoothing interval is programmed in PECI
Configuration Register 1 (0x36). Bits [2:0] of Register 0x36
set the duration over which the PECI data being read by the
ADT7490 is averaged. These bits set the duration over which
smoothing is carried out on the PECI data read. The refresh rate
in the PECI value registers is the same as the smoothing interval
programmed.
The smoothing interval is calculated using the following
formula:
Smoothing Interval = #reads × (tBIT × 67 × #CPU + tIDLE )
where:
#reads is the number of readings defined in Register 0x36,
Bits [2:0].
tBIT is the negotiated bit rate.
67 is the number of bits in each PECI reading.
#CPU is the number of CPUs providing PECI data (1 to 4).
tIDLE = 14 μs, the delay between consecutive reads.
For example,
#reads = 4096
tBIT = 1 μs (1 MHz speed)
#CPU = 1
Smoothing Interval = 331 ms = PECI reading refresh rate.
PECI Error Codes
There are two different error conditions for PECI data, PECI
data errors, and PECI bus communications errors. Table 12
describes the two different error conditions. If the ADT7490
reads an error code (0x8000 to 0x8003) from the CPU over the
PECI interface, Bit 1 is set in Interrupt Status 3 register (0x43),
indicating a data error. The value of the error code is not
included in the PECI value averaging sum. This means that a
value of 0x00 is added to the PECI sum when an error code is
recorded. The error code is not reported in the appropriate
PECI value register. If an invalid FCS is recorded by the
ADT7490, Bit 2 is set in the Interrupt Status 3 register (0x43),
indicating a communications error. An alert is generated on the
SMBALERT pin when either or both of these status bits are
asserted.
Rev. 0 | Page 19 of 76
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