ADT7316(RevPrN) Ver la hoja de datos (PDF) - Analog Devices

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ADT7316
(Rev.:RevPrN)

SPI/I2C® Compatible, 10-Bit Digital Temperature Sensor and Quad Voltage Output 12/10/8-Bit DAC

Analog Devices 

PRELIMINARY TECHNICAL DATA

FUNCTIONAL DESCRIPTION - DAC

The ADT7316/7317/7318 has quad resistor-string DACs

fabricated on a CMOS process with a resolutions of 12,

10 and 8 bits respectively. They contain four output buffer

amplifiers and is written to via I2C serial interface or SPI

serial interface. See Serial Interface Selection section for

more information.

ADT7316/7317/7318

Int VREF

BUF

V REFA B

REFERENCE

GA IN MODE

(GAIN=1 OR 2)

B UFF ER

The ADT7316/7317/7318 operates from a single supply

of 2.7 V to 5.5 V and the output buffer amplifiers provide

rail-to-rail output swing with a slew rate of 0.7V/µs.

DACs A and B share a common reference input, namely

VREFAB. DACs C and D share a common reference input,

namely VREFCD. Each reference input may be buffered to

draw virtually no current from the reference source, or

unbuffered to give a reference input range from GND to

VDD. The devices have a power-down mode, in which all

DACs may be turned off completely with a high-imped-

ance output.

Each DAC output will not be updated until it receives the

LDAC command. Therefore while the DAC registers

would have been written to with a new value, this value

will not be represented by a voltage output until the DACs

have received the LDAC command. Reading back from

any DAC register prior to issuing an LDAC command

will result in the digital value that corresponds to the

DAC output voltage. Thus the digital value written to the

DAC register cannot be read back until after the LDAC

command has been initiated. This LDAC command can

be given by either pulling the LDAC pin low, setting up

Bits D4 and D5 of DAC Configuration register(Address =

1Bh) or using the LDAC register(Address = 1Ch).

Digital-to-Analog Section

The architecture of one DAC channel consists of a resis-

tor-string DAC followed by an output buffer amplifier.

The voltage at the VREF pin or the on-chip reference of

2.25 V provides the reference voltage for the correspond-

ing DAC. Figure 7 shows a block diagram of the DAC

architecture. Since the input coding to the DAC is straight

binary, the ideal output voltage is given by:

VREF * D

VOUT = ----------

2N

where D=decimal equivalent of the binary code which is

loaded to the DAC register;

0-255 for ADT7318 (8-Bits)

0-1023 for ADT7317 (10-Bits)

0-4095 for ADT7316 (12-Bits)

N = DAC resolution.

INP UT

REG IS TE R

DAC

REGISTER

RESISTOR

STRING

VO UTA

OUTPUT BUFFER

A MP LI FI ER

Figure 7. Single DAC channel architecture

Resistor String

The resistor string section is shown in Figure 9. It is sim-

ply a string of resistors, each of value R. The digital code

loaded to the DAC register determines at what node on

the string the voltage is tapped off to be fed into the out-

put amplifier. The voltage is tapped off by closing one of

the switches connecting the string to the amplifier. Be-

cause it is a string of resistors, it is guaranteed monotonic.

DAC Reference Inputs

There is a reference pin for each pair of DACs. The refer-

ence inputs are buffered but can also be individually con-

figured as unbuffered.

VRE F- AB

2 . 25 V

Intern al V

R EF

S TRI NG

DAC A

S TRI NG

DAC B

Figure 8. DAC Reference Buffer Circuit

The advantage with the buffered input is the high imped-

ance it presents to the voltage source driving it. However

if the unbuffered mode is used, the user can have a refer-

ence voltage as low as 0.25 V and as high as VDD since

there is no restriction due to headroom and footroom of

the reference amplifier.

REV. PrN

–13–

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