ADSP-21365SBBC-ENG Ver la hoja de datos (PDF) - Analog Devices

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ADSP-21365SBBC-ENG

SHARC® Processor

Analog Devices 

Preliminary Technical Data

Clock Input

Table 11. Clock Input

Parameter

Min

Timing Requirements

tCK

CLKIN Period

181

tCKL

CLKIN Width Low

7.51

tCKH

CLKIN Width High

7.51

tCKRF

CLKIN Rise/Fall (0.4V–2.0V)

tCCLK3

CCLK Period

3.01

1 Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

2 Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.

3 Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.

333 MHz

Max

TBD2

TBD2

TBD2

TBD

TBD

CLKIN

tCKH

tCK

tCKL

Figure 7. Clock Input

Clock Signals

The ADSP-21365/6 can use an external clock or a crystal. See

the CLKIN pin description in Table 3 on page 11. The program-

mer can configure the ADSP-21365/6 to use its internal clock

generator by connecting the necessary components to CLKIN

and XTAL. Figure 8 shows the component connections used for

a crystal operating in fundamental mode. Note that the clock

rate is achieved using a 16.67 MHz crystal and a PLL multiplier

ratio 16:1 (CCLK:CLKIN achieves a clock speed of 266 MHz).

To achieve the full core clock rate, programs need to configure

the multiplier bits in the PMCTL register.

CLKIN

1M⍀

XTAL

C1

X1

C2

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL

SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

Figure 8. 333 MHz Operation (Fundamental Mode Crystal)

ADSP-21365/6

Unit

ns

ns

ns

ns

ns

Rev. PrA | Page 19 of 54 | September 2004

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