ADSP-21266SKSTZ-1C Ver la hoja de datos (PDF) - Analog Devices

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ADSP-21266SKSTZ-1C

SHARC® Embedded Processor

Analog Devices 

Timer PWM_OUT Cycle Timing

The timing specification in Table 15 and Figure 12 applies to

Timer in PWM_OUT (pulse-width modulation) mode. Timer

signals are routed to the DAI_P20–1 pins through the SRU.

Therefore, the timing specifications provided below are valid at

the DAI_P20–1 pins.

Table 15. Timer PWM_OUT Timing

Parameter

Switching Characteristic

tPWMO

Timer Pulse Width Output

Min

2 tCCLK – 1

Max

2(231 – 1) tCCLK

DAI_P20–1

(TIMER)

tPWMO

Figure 12. Timer PWM_OUT Timing

Timer WDTH_CAP Timing

The timing specification in Table 16 and Figure 13 applies to

Timer in WDTH_CAP (pulse width count and capture) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 16. Timer Width Capture Timing

Parameter

Timing Requirement

tPWI

Timer Pulse Width

Min

2 tCCLK

Max

2(231 – 1) tCCLK

DAI_P20–1

(TIMER)

tPWI

Figure 13. Timer Width Capture Timing

ADSP-21266

Unit

ns

Unit

ns

Rev. B | Page 21 of 44 | May 2005

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