AD9852ASVZ(RevF) Ver la hoja de datos (PDF) - Analog Devices
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AD9852ASVZ Datasheet PDF : 41 Pages
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Data Sheet
AD9852
Figure 10 to Figure 15 show the trade-off in elevated noise floor, increased phase noise (PN), and discrete spurious energy when the
internal REFCLK multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown. Compare the noise floor of
Figure 11 and Figure 12 with that of Figure 14 and Figure 15. The improvement seen in Figure 11 and Figure 12 is a direct result of sampling
the fundamental at a higher rate. Sampling at a higher rate spreads the quantization noise of the DAC over a wider bandwidth, which
effectively lowers the noise floor.
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 39.1MHz
100kHz/
SPAN 1MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 39.1MHz
100kHz/
SPAN 1MHz
Figure 10. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,
300 MHz REFCLK with REFCLK Multiplier Bypassed
Figure 13. Narrow-Band SFDR, 39.1 MHz, 1 MHz BW,
30 MHz REFCLK with REFCLK Multiplier = 10×
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 39.1MHz
5kHz/
SPAN 50kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 39.1MHz
5kHz/
SPAN 50kHz
Figure 11. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
300 MHz REFCLK with REFCLK Multiplier Bypassed
Figure 14. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
30 MHz REFCLK with REFCLK Multiplier = 10×
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 39.1MHz
5kHz/
SPAN 50kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CENTER 39.1MHz
5kHz/
SPAN 50kHz
Figure 12. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
100 MHz REFCLK with REFCLK Multiplier Bypassed
Figure 15. Narrow-Band SFDR, 39.1 MHz, 50 kHz BW,
10 MHz REFCLK with REFCLK Multiplier = 10×
Rev. F | Page 13 of 41
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