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AD9628-125EBZ Datasheet PDF : 42 Pages
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AD9628
Data Sheet
AD9628-105
AD9628-125
Parameter1
Temp Min
Typ
Max
Min
Typ
Max
Unit
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
25°C
92
92
dBc
fIN = 30.5 MHz
25°C
90
90
dBc
fIN = 70 MHz
25°C
90
93
dBc
Full 82
85
dBc
fIN = 100 MHz
25°C
89
90
dBc
fIN = 200 MHz
25°C
83
84
dBc
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
25°C
−96
−94
dBc
fIN = 30.5 MHz
25°C
−95
−94
dBc
fIN = 70 MHz
25°C
−95
−95
dBc
Full
−87
−87
dBc
fIN = 100 MHz
25°C
−93
−92
dBc
fIN = 200 MHz
25°C
−92
−91
dBc
TWO-TONE SFDR
fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C
85
85
dBc
CROSSTALK2
Full
−95
−95
dB
ANALOG INPUT BANDWIDTH
25°C
650
650
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS/SYNC)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
Temp
AD9628-105/AD9628-125
Min
Typ Max
CMOS/LVDS/LVPECL
Full
0.9
Full
0.3
3.6
Full
AGND − 0.3
AVDD + 0.2
Full
0.9
1.4
Full
−10
+10
Full
−10
+10
Full
4
Full
8
10
12
Full
1.22
Full
0
Full
−10
Full
40
Full
Full
DRVDD + 0.2
0.6
+10
132
26
2
Full
1.22
Full
0
Full
−92
Full
−10
Full
Full
Rev. C | Page 6 of 42
DRVDD + 0.2
0.6
−135
+10
26
2
Unit
V
V p-p
V
V
µA
µA
pF
kΩ
V
V
µA
µA
pF
V
V
µA
µA
pF

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