AD9553/PCBZ Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

fabricante

AD9553/PCBZ

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet

Analog Devices 

AD9553

OUTPUT CHARACTERISTICS

Table 8.

Parameter

LVPECL MODE

Differential Output Voltage Swing

Common-Mode Output Voltage

Frequency Range

Duty Cycle

Rise/Fall Time1 (20% to 80%)

LVDS MODE

Differential Output Voltage Swing

Balanced, VOD

Unbalanced, ΔVOD

Offset Voltage

Common Mode, VOS

Common-Mode Difference, ΔVOS

Short-Circuit Output Current

Frequency Range

Duty Cycle

Rise/Fall Time1 (20% to 80%)

CMOS MODE

Output Voltage High, VOH

IOH = 10 mA

IOH = 1 mA

Output Voltage Low, VOL

IOL = 10 mA

IOL = 1 mA

Frequency Range

Duty Cycle

Rise/Fall Time1 (20% to 80%)

Min

Typ

Max

Unit Test Conditions/Comments

690

800

890

mV Output driver static (for dynamic performance, see

Figure 18)

VDD − 1.66 VDD − 1.34 VDD − 1.01 V

Output driver static

0

810

MHz

40

60

% Up to 805 MHz output frequency

255

305

ps 100 Ω termination between both pins of the

output driver

Output driver static (for dynamic performance, see

Figure 18)

297

398

mV Voltage swing between the pins of a differential

output pair with the output driver static

8.3

mV Absolute difference between voltage swing of

normal pin and inverted pin with the output

driver static

1.17

17

0

40

285

1.35

V

(VOH + VOL)/2 across a differential pair with output

driver static

7.3

mV This is the absolute value of the difference

between VOS when the normal output is high vs.

when the complementary output is high with

output driver static

24

mA Output shorted to GND

810

MHz

60

% Up to 805 MHz output frequency

355

ps 100 Ω termination between both pins of the

output driver

Output driver static; standard drive strength setting

2.8

V

2.8

V

Output driver static; standard drive strength setting

0.5

V

0.3

V

0

200

MHz 3.3 V CMOS; standard drive strength setting;

output toggle rates in excess of the maximum are

possible, but with reduced amplitude (see Figure 17)

45

55

% At maximum output frequency

500

745

ps 3.3 V CMOS; standard drive strength setting;

10 pF load

1 The listed values are for the slower edge (rise or fall).

Rev. A | Page 6 of 44

Share Link: