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AD9553

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet

Analog Devices 

AD9553

SPI/OM[2:0]

3

10

3

3

SPI MODE

A[3:0]

4

Y[5:0]

6

FREQUENCY

SELECTION

PINS DECODER

SPI CONTROLLER

OUTPUT

MODE

CONTROL

DECODER

3

OUTPUT

MODE

ENABLE SPI CONTROL

OF OUTPUT MODE

CONTROL

FUNCTION

0

BITS

3

1

ENABLE SPI CONTROL

OF OUTPUT ABC BITS

FUNCTION

ABC BITS

0

1

OUTPUT MODE

CONTROL

FUNCTION

FUNCTION

ABC

FUNCTION

XYZ BITS

ENABLE SPI CONTROL

OF FUNCTIONING XYZ

0

FUNCTION

1

XYZ

REGISTER MAP

FUNCTION

MUXES

Figure 28. Control Mode Diagram

Although the SPI and pin control modes are functionally

independent, it is possible to mix the control modes. For

example, suppose that pin control satisfies all of the require-

ments for an application except for the value of the P2 divider

(which is associated with OUT2). The user could do the

following:

• Activate SPI mode via the frequency selection pins.

• Program the desired P0, P1, and P2 values in the register

map (Register 0x15 to Register 0x18).

• Set the enable SPI control bit for the output dividers

(Register 0x14[2] = 1).

• Calibrate the VCO by enabling SPI control of VCO

calibration (Register 0x0E[2] = 1), then issue a calibrate

command (Register 0x0E[7] = 1). Be sure to program the

N divider, R dividers, ÷5 dividers, and ×2 multipliers to the

values defined by the Ax and Yx pin settings prior to cali-

brating the VCO.

• Restore the original settings to the frequency selection pins

to invoke the desired frequency selection.

In this way, the function muxes that control P0, P1, and P2 select

the appropriate register bits as the source for controlling the

dividers, while all the other function muxes select the pin decoders

as the source for controlling the other functions. Note that the

dividers remain under register control until the user activates

SPI mode and writes Register 0x14[2] = 0, thereby causing the

function mux to use the frequency selection pins decoder as the

source for controlling the dividers, instead of the register map.

DESCRIPTION OF FUNCTIONAL BLOCKS

Reference Inputs

The default configuration of the AD9553 provides up to two

single-ended input clock receivers, REFA and REFB, which are

high impedance CMOS inputs. In applications that require redun-

dant reference clocks with switchover capability, REFA is the

primary reference and REFB the secondary reference. Alternatively,

the user can configure the input (via the serial I/O port) as a

single differential receiver. In this case, the REFB input func-

tions as REFA (the complementary input of REFA). Note that

in this configuration the device operates with only one reference

input clock, eliminating the need for switchover functionality.

XTAL Input

The AD9553 accepts an optional 25 MHz crystal resonator

connected across the XTAL pins. Alternatively, it accepts a

single-ended clock source (CMOS compatible) connected to

either one of the XTAL input pins (in this case, the unused

input remains floating). Unless otherwise programmed, the

device expects the crystal to have a specified load capacitance

of 10 pF (default). The AD9553 provides the necessary load

capacitance internally. The internal load capacitance consists

Rev. A | Page 20 of 44

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