AD9552BCPZ(RevC) Ver la hoja de datos (PDF) - Analog Devices
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AD9552BCPZ Datasheet PDF : 32 Pages
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AD9552
SERIAL CONTROL PORT
Table 5.
Parameter
CS
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO
Input
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output
Output Logic 1 Voltage
Output Logic 0 Voltage
Min
Typ
1.6
2
2
1.6
2
2
1.6
1
1
2
2.8
SERIAL CONTROL PORT TIMING
Table 6.
Parameter
SCLK
Clock Rate, 1/tCLK
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO, tDV
CS to SCLK Setup (tS) and Hold (tH)
CS Minimum Pulse Width High
Limit
50
3
3
4
0
13
0
6.4
Max
Unit
Test Conditions/Comments
V
0.5
V
0.03
μA
μA
pF
V
0.5
V
μA
0.03
μA
pF
V
0.5
V
μA
μA
pF
V
0.3
V
1 mA load current
1 mA load current
Unit
MHz max
ns min
ns min
ns min
ns min
ns max
ns min
ns min
Rev. C | Page 6 of 32
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