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AD9245BCPZ-80
(Rev.:RevE)

14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter

Analog Devices 

AD9245

VIN+

VIN–

+

10F 0.1F

VREF

R2

SENSE

SELECT

LOGIC

ADC

CORE

REFT

0.1F

0.1F

REFB

0.1F

+ 10F

R1

0.5V

AD9245

Figure 47. Programmable Reference Configuration

EXTERNAL REFERENCE OPERATION

The use of an external reference can be necessary to enhance

the gain accuracy of the ADC or improve thermal drift char-

acteristics. When multiple ADCs track one another, a single

reference (internal or external) can be necessary to reduce

gain matching errors to an acceptable level. Figure 48 shows

the typical drift characteristics of the internal reference in both

1.0 V and 0.5 V modes.

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7 kΩ load. The internal buffer still generates the positive and

negative full-scale references, REFT and REFB, for the ADC

core. The input span is always twice the value of the reference

voltage; therefore, the external reference must be limited to a

maximum of 1.0 V.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

VREF = 1.0V

0.2

0.1

VREF = 0.5V

0

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

TEMPERATURE (°C)

Figure 48. Typical VREF Drift

Data Sheet

OPERATIONAL MODE SELECTION

As discussed earlier, the AD9245 can output data in either

offset binary or twos complement format. There is also a

provision for enabling or disabling the clock DCS. The

MODE pin is a multilevel input that controls the data format

and DCS state. The input threshold values and corresponding

mode selections are outlined in Table 11.

Table 11. Mode Selection

MODE Voltage Data Format

AVDD

Twos Complement

2/3 AVDD

Twos Complement

1/3 AVDD

Offset Binary

AGND (Default) Offset Binary

Duty Cycle Stabilizer

Disabled

Enabled

Enabled

Disabled

EVALUATION BOARD

The AD9245 evaluation board provides the support circuitry

required to operate the ADC in its various modes and

configurations. Complete schematics and layout plots follow

and demonstrate the proper routing and grounding techniques

that should be applied at the system level.

It is critical that signal sources with very low phase noise

(<1 ps rms jitter) be used to realize the ultimate performance of

the converter. Proper filtering of the input signal, to remove

harmonics and lower the integrated noise at the input, is also

necessary to achieve the specified noise performance.

The AD9245 can be driven single-ended or differentially

through a transformer. Separate power pins are provided to

isolate the DUT from the support circuitry. Each input

configuration can be selected by proper connection of

various jumpers (refer to the schematics).

An alternative differential analog input path using an

AD8351 op amp is included in the layout but is not populated

in production. Designers interested in evaluating the op amp

with the ADC should remove C15, R12, and R3 and populate

the op amp circuit. The passive network between the AD8351

outputs and the AD9245 allows the user to optimize the

frequency response of the op amp for the application.

Rev. E | Page 22 of 32

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