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AD9219-65EB

Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter

Analog Devices 

TIMING DIAGRAMS

N–1

AD9219

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D–

D+

tA

tEH

N

tEL

tCPD

tFCO

tFRAME

tPD

tDATA

MSB D8

D7 D6

D5

D4 D3

D2

D1 D0 MSB D8

D7

D6

D5

N–10 N–10 N–10 N–10 N–10 N–10 N–10 N–10 N–10 N–10 N–9 N–9 N–9 N–9 N–9

Figure 2. 10-Bit Data Serial Stream (Default)

AIN

CLK–

CLK+

DCO–

DCO+

FCO–

FCO+

D–

D+

N-1

tA

tEH

N

tEL

tCPD

tFCO

tFRAME

tPD

tDATA

MSB D10 D9

D8 D7 D6

D5

D4

D3

D2

D1

D0 MSB D10

N – 10 N – 10 (N – 10) N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 9 N – 9

Figure 3. 12-Bit Data Serial Stream

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