AD9219-65EB Ver la hoja de datos (PDF) - Analog Devices
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AD9219-65EB Datasheet PDF : 52 Pages
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AD9219
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter 1
CLOCK 2
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS2
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)3
DCO to Data Delay (tDATA)3
DCO to FCO Delay (tFRAME)3
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power Down)
Pipeline Latency
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
AD9219-40
Min
Typ
Max
40
10
12.5
12.5
2.0
2.0
(tSAMPLE/20) − 300
(tSAMPLE/20) − 300
2.5
300
300
2.5
tFCO +
(tSAMPLE/20)
(tSAMPLE/20)
(tSAMPLE/20)
±50
3.5
3.5
(tSAMPLE/20) + 300
(tSAMPLE/20) + 300
±150
600
375
10
AD9219-65
Min
Typ
Max
65
10
7.7
7.7
2.0
2.0
(tSAMPLE/20) − 300
(tSAMPLE/20) − 300
2.5
300
300
2.5
tFCO +
(tSAMPLE/20)
(tSAMPLE/20)
(tSAMPLE/20)
±50
3.5
3.5
(tSAMPLE/20) + 300
(tSAMPLE/20) + 300
±150
600
375
10
APERTURE
Aperture Delay (tA)
25°C
500
500
Aperture Uncertainty (Jitter) 25°C
<1
<1
Out-of-Range Recovery Time 25°C
1
2
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
ns
μs
CLK
cycles
ps
ps rms
CLK
cycles
1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
2 Can be adjusted via the SPI interface.
3 tSAMPLE/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
Rev. 0 | Page 6 of 52
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