AD8324ACPZ(RevC) Ver la hoja de datos (PDF) - Analog Devices
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AD8324ACPZ Datasheet PDF : 16 Pages
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Data Sheet
AD8324
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1
GND 2
VIN+ 3
VIN– 4
GND 5
AD8324
TOP VIEW
(Not to Scale)
15 RAMP
14 VOUT+
13 VOUT–
12 BYP
11 NIC
NOTES
1. NIC = NO INTERNAL CONNECTION. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MUST BE CONNECTED TO A
SOLID COPPER PLANE WITH A LOW THERMAL
RESISTANCE. THIS APPLIES TO THE 20-LEAD LFCSP
PACKAGE ONLY.
Figure 5. 20-Lead LFCSP Pin Configuration
GND 1
20 GND
VCC 2
GND 3
19 VCC
18 TXEN
GND
VIN+
VIN–
GND
4 AD8324 17 RAMP
5 TOP VIEW 16 VOUT+
6 (Not to Scale) 15 VOUT–
7
14 BYP
DATEN 8
13 NIC
SDATA 9
12 SLEEP
CLK 10
11 GND
NOTES
1. NIC = NO INTERNAL CONNECTION.
DO NOT CONNECT TO THIS PIN.
Figure 6. 20-Lead QSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
20-Lead LFCSP 20-Lead QSOP Mnemonic
1, 2, 5, 9, 18, 19 1, 3, 4, 7, 11, 20 GND
3
5
VIN+
4
6
VIN–
6
8
DATEN
7
8
10
11
12
13
14
15
16
17, 20
0
9
SDATA
10
CLK
12
SLEEP
13
14
15
16
17
18
2, 19
Not applicable
NIC
BYP
VOUT–
VOUT+
RAMP
TXEN
VCC
EPAD
Description
Common External Ground Reference.
Noninverting Input. DC-biased to approximately VCC/2. Must be ac-coupled with a 0.1 μF
capacitor.
Inverting Input. DC-biased to approximately VCC/2. Must be ac-coupled with a 0.1 μF
capacitor.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A
Logic 0 to Logic 1 transition transfers the latched data to the attenuator core (updates the
gain) and simultaneously inhibits serial data transfer into the register. A Logic 1 to
Logic 0 transition inhibits the data latch (holds the previous and simultaneously
enables the register for serial data load).
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into
the internal register with the most significant bit (MSB) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit
master-slave shift register. Logic 0 to Logic 1 transition latches the data bit, and a
Logic 1 to Logic 0 transfers the data bit to the slave. This requires the input serial
data-word to be valid at or before this clock transition.
Low Power Sleep Mode. In sleep mode, the supply current of the AD8324 is reduced
to 30 μA. A Logic 0 powers down the device (high ZOUT state), and a Logic 1 powers
up the device.
No Internal Connection. Do not connect to this pin.
Internal Bypass. This pin must be externally decoupled (0.1 μF capacitor).
Negative Output Signal. Must be biased to VCC. See Figure 23.
Positive Output Signal. Must be biased to VCC. See Figure 23.
External RAMP Capacitor (Optional).
Transmit Enable. Logic 0 disables forward transmission, and Logic 1 enables forward
transmission.
Common Positive External Supply Voltage.
Exposed Pad. The exposed pad must be connected to a solid copper plane with low
thermal resistance. This applies to the 20-lead LFCSP package only.
Rev. C | Page 7 of 16
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