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AD8193ACPZ

Buffered 2:1 TMDS Switch

Analog Devices 

AD8193

OUTPUT CHANNELS

Each high speed output differential pair is terminated to the

3.3 V VTTO power supply through two single-ended 50 Ω

on-chip resistors, as shown in Figure 20. These matched on-

chip back-terminations absorb reflections on the output TMDS

channels and improve the overall system signal integrity. These

termination resistors are always present in the outputs and they

cannot be switched out.

VTTO

50Ω

50Ω

OP[3:0]

ON[3:0]

IOUT

AVEE

Figure 20. High Speed Output Simplified Schematic

In a typical application, the AD8193 output is connected to the

input of an HDMI/DVI receiver, which provides a second set of

matched terminations in accordance with the HDMI 1.3

specification. If no receiver is connected, each of the AD8193

output pins should be tied to 3.3 V through a 50 Ω on-board

termination resistor.

Data Sheet

SWITCHING MODE

The source selector pin, S_SEL, is used to select which of the

two input groups is routed to the output. Source A is selected

when S_SEL is pulled up to logic high, and Source B is selected

when S_SEL is pulled down to logic low. Logic levels for this pin

are set in accordance with the specifications listed in Table 5. The

AD8193 can be used as a single-link TMDS buffer by setting

S_SEL to one fixed logic value.

S_SEL also controls the switch status of the input termination

resistors. The termination resistors for the selected input are

always connected, whereas the termination resistors for the

unselected input are always switched out (high-Z inputs).

Table 5. S_SEL Description

Selected

S_SEL Input

Input Termination Status

0

Input B

Input B terminations enabled, Input A

terminations disabled

1

Input A

Input A terminations enabled, Input B

terminations disabled

Rev. A | Page 10 of 16

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