AD7927BRU Ver la hoja de datos (PDF) - Analog Devices
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AD7927BRU Datasheet PDF : 29 Pages
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Data Sheet
AD7927
SPECIFICATIONS
AVDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK = 20 MHz; TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)2
Signal-to-Noise Ratio (SNR)2
Total Harmonic Distortion (THD) 2
Peak Harmonic or Spurious Noise
(SFDR) 2
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Channel-to-Channel Isolation2
Full Power Bandwidth
DC ACCURACY2
Resolution
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
Offset Error Match
Gain Error
Gain Error Match
0 V to 2 × REFIN Input Range
Positive Gain Error
Positive Gain Error Match
Zero Code Error
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN3
B Version1
Unit
70
dB min
69.5
dB min
69
dB min
70
dB min
69.5
dB min
−77
dB max
−73
dB max
−78
dB max
−76
dB max
−90
dB typ
−90
dB typ
10
ns typ
50
ps typ
−82
dB typ
8.2
MHz typ
1.6
MHz typ
12
±1
−0.9/+1.5
Bits
LSB max
LSB max
±8
LSB max
±0.5
LSB max
±1.5
LSB max
±0.5
LSB max
±1.5
LSB max
±0.5
LSB max
±8
LSB max
±0.5
LSB max
±1
LSB max
±0.5
LSB max
0 to REFIN
0 to 2 × REFIN
±1
20
V
V
μA max
pF typ
2.5
V
±1
μA max
36
kΩ typ
0.7 × VDRIVE
0.3 × VDRIVE
±1
10
V min
V max
μA max
pF max
Rev. D | Page 3 of 28
Test Conditions/Comments
fIN = 50 kHz sine wave, fSCLK = 20 MHz
@ 5 V, B models
@ 5 V, W models
@ 3 V Typically 70 dB
B models
W models
@ 5 V Typically −84 dB
@ 3 V Typically −77 dB
@ 5 V Typically −86 dB
@ 3 V Typically −80 dB
fA = 40.1 kHz, fB = 41.5 kHz
fIN = 400 kHz
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to 12 bits
Straight binary output coding
Typically ±0.5 LSB
−REFIN to +REFIN biased about REFIN with
Twos complement output coding
Typically ±0.8 LSB
RANGE bit set to 1
RANGE bit set to 0, AVDD/VDRIVE = 4.75 V to 5.25 V
fSAMPLE = 200 kSPS
±1% specified performance
Typically 10 nA, VIN = 0 V or VDRIVE
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