CS
SCLK
DIN
RDY
CS
SCLK
DOUT
ISINK (1.6mA WITH VDD = 5V
100A WITH VDD = 3V)
TO OUTPUT
PIN
50pF
1.6V
ISOURCE (200A WITH VDD = 5V
100A WITH VDD = 3V)
Figure 1. Load Circuit for Timing Characterization
AD7709
t11
t12
t13
MSB
t14
t15
Figure 2. Write Cycle Timing Diagram
t3
t4
t6
t5
t7
t5A
MSB
Figure 3. Read Cycle Timing Diagram
t16
LSB
t10
t8
t9
LSB
REV. A
–7–