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AD7298
(Rev.:RevPrA)

8-Channel, 1MSPS, 12-Bit SAR ADC with Temperature Sensor

Analog Devices 

AD7298

SERIAL INTERFACE

Figure 13 shows the detailed timing diagram for the serial

interface to the AD7298. The serial clock provides the

conversion clock and controls the transfer of information to and

from the AD7298 during each conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track-and-hold into hold mode

at which point the analog input is sampled and the bus is taken

out of three-state. The conversion is also initiated at this point

and requires 16 SCLK cycles to complete. The track-and-hold

goes back into track on the 14th SCLK falling edge as shown in

Figure 13 at Point B. On the 16th SCLK falling edge or on the

rising edge of CS , the DOUT line goes back into three-state. If the

rising edge of CS occurs before 16 SCLKs have elapsed, the

conversion is terminated, the DOUT line goes back into tri-state,

and the control register is not updated; otherwise DOUT returns

to three-state on the 16th SCLK falling edge. Sixteen serial clock

cycles are required to perform the conversion process and to

access data from the AD7298.

For the AD7298, four-channel address bits (ADD3 to ADD0)

identify which channel the conversion result corresponds, to

precede the 12 bits of data. The CS going low provides the first

address bit to be read in by the microcontroller or DSP. The

Preliminary Technical Data

remaining data is then clocked out by subsequent SCLK falling

edges, beginning with a second address bit. Thus, the first

falling clock edge on the serial clock has the first address bit

provided for reading and also clocks out the second address bit.

The 3 remaining address bits and 12 data bits are clocked out by

subsequent SCLK falling edges. The final bit in the data transfer

is valid for reading on the 16th falling edge having been clocked

out on the previous (15th) falling edge.

In applications with a slower SCLK, it may be possible to read

in data on each SCLK rising edge depending on the SCLK

frequency. The first rising edge of SCLK after the CS falling

edge would have the first address bit provided, and the 15th

rising SCLK edge would have last data bit provided.

Writing information to the control register takes place on the

first 16 falling edges of SCLK in a data transfer, assuming the MSB

(that is, the WRITE bit) has been set to 1. The 16-bit word read

from the AD7298 always contains four channel address bits that

the conversion result corresponds to, followed by the 12-bit

conversion result.

Figure 13. Serial Interface Timing Diagram

TEMPERATURE SENSOR READ.

The temperature sensor conversion involves two phases, the

integration phase and the conversion phase as detailed in the

Temperature Sensor Operation Section. The integration phase

is initiated on the falling edge of CS and once completed the

conversion is automatically initiated internally by the AD7298.

When a temperature conversion integration is initiated, the

TSENSEBUSY signal goes high to indicate that a temperature

conversion is in progress and remains high until the conversion

is completed.

The total time to measure and convert a temperature channel

with the AD7298 is 100 μs max. Once the TSENSEBUSY signal

goes low to indicate that the temperature conversion is

completed, t11ns must elapse prior to the next falling edge of CS.

If a minimum of t11 ns is not adhered to between the falling

edge of TSENSEBUSY and the subsequent falling edge of CS, the

next conversion will be corrupted but the temperature result

that is framed by the CS will not be affected. This restriction is

in place to ensure that sufficient acquisition time is allowed for

the next conversion.

Rev. PrA | Page 16 of 18

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